Phase-Locked Loop Circuit Design Dan H. Wolaver
Publisher: Prentice Hall

Other carrier-grade features include SONET-compatible jitter peaking (0.1dB max) and circuitry to minimise output clock phase transients during reference switching. The part about the circuit design is the part which scares me, because I don't have any experience with circuit design. 20 MHz Dual Trace Oscilloscope 3. I've read a lot of theory and math about Phase Locked Loops. Analog FastSPICE™ Platform Delivers Silicon-Accurate 300fs Jitter PLL Characterization. Before clock multiplier circuits existed, they had to be implemented with discrete parts. Cosmic Circuits today announced that its PLL solutions are being used by Enverv, a provider of advanced SoC solutions for smart grid, metering and control applications. ICS501 – Integrated PLL Clock Multiplier. This took up quite a bit time in design and prototyping. Set the Oscilloscope for the following settings: Channel 1-1V/division, Time base: 0.5ms/division 2. PHASE LOCKED LOOP,Ask Latest information,Abstract,Report,Presentation (pdf,doc,ppt),PHASE LOCKED LOOP technology discussion,PHASE LOCKED LOOP paper presentation details. Patch the circuit as shown in the wiring diagram and apply power to the trainer. Patch Chords & CRO Probes Procedure: 1. Calendar October 5, 2012 | Posted by KF5OBS. BH1417 – Stereo PLL Transmitter IC (Case SOP22) 1x 7.6MHz Crystal 1x MPSA13 – NPN Darlington Transistor 1x 2.5 Turns Variable Coil 1x MV2109 – Varicap Diode 1x 4-DIP Switch ANT – 30 cm of copper wire.